delic-lc/delic-pb dsp embedded line and port interface controller peb 20570/peb 20571/pef 20570/pef 20571 version 3.1 ds2.1, 2003-08-04 addendum 1/8 2003-08-04 addendum 1addendum to ?del ic clock system synchronization? the delic clock system synchronization is described in the delic-lc peb 20570/ delic-pb peb 20571 data sheet, independent of the version (2.1 .. 3.1). as an addendum to chapter ?delic clock system synchronization? of the delic- lc/delic-pb data sheet the following describes the system behaviour when using the vip peb 20590 or peb 20591 in lt-t mode , for example when synchronizing to the central office. note: ocem ? and oakdspcore ? (oak ? ) are registered trademarks of parthusceva, inc.. revision history: previous version: addendum ds2, 2002-08-09 major changes: - chapter 3: new pef version of delic-lc/delic-pb is available - chapter 4: delic strap option configuration - trademarks changed
peb 20570/pef 20570 peb 20571/pef 20571 addendum to ?delic clock system synchronization? addendum 2/8 2003-08-04 1.1 clocking the vip in lt-t mode by delic layer 1 clock figure 1 clocking the vip by using delic layer 1 clock when the central office is activated, its clock signal is retrieved by the rxpll of the vip and a 1.536 mhz reference signal is generated and used as input signal for the delic dcxo (pin xclk). this signal is divided down to 8 khz and used as input for the dcxo phase detector (pd). the second input to pd is another 8 khz signal which originates from the 16.384 mhz output of the dcxo. the delic pll multiplies the 16.384 mhz dcxo signal up to 61.44 mhz. a divider generates the 15.36 mhz layer 1 clock which is used to clock the vip. when the central office is deactivated, the vip takes its oscillator signal of 15.36 mhz (the delic layer 1 clock) divided by 10 and uses this signal as delic xclk input as replacement of the central office clock. as a consequence, the delic dcxo gets its own signal as input for the pd. since the second pd input is also generated by the dcxo, the pll system is unstable. this results in the dcxo and the pll running to its respective corner frequency. therefore, the 100 ppm clock accuracy, required by itu-t i.430, cannot be guaranteed during this time. when switching to another clock source (refclk), the delic dcxo will work properly again. delic_refclk1 vip central office osc rxpll dcxo /10 mux 15.36 mhz 16.384 mhz divider pd pll divider 1.536 mhz divider 8khz xclk refclk 16.384 mhz delic l1_clk in clk mux refclk
peb 20570/pef 20570 peb 20571/pef 20571 addendum to ?delic clock system synchronization? addendum 3/8 2003-08-04 the time within the delic dcxo guarantees the 100 ppm clock accuracy varies, depending on various conditions. when the central office deactivates, the user will be notified by the delic. it is up to the user to provide another clock source (for example refclk) for the dcxo as soon as possible. 1.2 vip clocked in lt-t mode by an external crystal figure 2 clocking the vip by using external crystal as shown in figure 2 no unstable system can occur by using an external crystal rather than the delic layer 1 clock as vip clock source in lt-t mode. when the central office line is deactivated, the vip takes the 15.36 mhz oscillator signal and divides it by 10. this signal is used as xclk input of the delic dcxo. since the vip 15.36 mhz signal is entirely independent from the delic clocking system no unstable system can occur. note: in lt-t mode it is recommended to use an external crystal to clock the vip. delic_refclk2 vip central office osc rxpll dcxo /10 mux 15.36 mhz 16.384 mhz divider pd pll divider 1.536 mhz divider 8khz xclk refclk 16.384 mhz delic mux refclk
peb 20570/pef 20570 peb 20571/pef 20571 corrections to ?recommended 16.384 mhz crystal addendum 4/8 2003-08-04 2 corrections to ?recomm ended 16.384 mhz crystal parameters? the following table and figures should be taken as an replacement of the ?recommended 16.384 mhz crystal parameters? of the delic-lc peb 20570/pef 20570 and delic-pb peb 20571/pef 20571. the delic pll pulls the external crystal by adding/substracting capacitors (internal). by default, half of the internal capacitors are switched on at each pin (clk16_xi and clk_16xo). figure 3 connecting the crystal to the delic attention: on the delic evaluation board (smart 2057, infineon) c x1 and c x2 are 3.3 pf each. this value can be used as reference, but depends on the respective board design (for example layout). delic_quartz1 c x1 c x2 delic clk16_xo clk16_xi
peb 20570/pef 20570 peb 20571/pef 20571 corrections to ?recommended 16.384 mhz crystal addendum 5/8 2003-08-04 figure 4 equivalent circuit diagram of the crystal table 1 recommend crystal parameters parameter symbol values unit motional capacitance c 1 > 25 ff shunt capacitance c 0 7pf external load capacitance c l 15 pf resonance resistance r 1 30 ? frequency calibration tolerance 150 ppm delic_quartz2 r l c c cc x1 x2 0 1 1 1
peb 20570/pef 20570 peb 20571/pef 20571 extended temperature range addendum 6/8 2003-08-04 3 extended temperature range the delic-lc and delic-pb, version 3.1, are now available as pef version. the pef version is compliant to the device description in the ? delic-lc peb 20570/delic-pb peb 20571 data sheet, version 3.1 ? but extends the operating conditions to the extended temperature range of -40c to +85c. the ordering code is: table 2 delic-lc/delic-pb pef version ordering code device name version type ordering code delic-lc version 3.1 pef 20570 q67237-h1442 delic-pb version 3.1 pef 20571 q67237-h1441
peb 20570/pef 20570 peb 20571/pef 20571 delic strap option configuration addendum 7/8 2003-08-04 4 delic strap opti on configuration the delic ? strap status register (cstrap) ? is described in the delic-lc peb 20570/delic-pb peb 20571 data sheet, independent of the version (2.1 .. 3.1). the register description (see updated register cstrap ) of the data sheet is misleading concerning bit 0 and 1. they are not configured by strap option. for a stable dcxo synchronization it is recommended to proceed as follows: 1. after boot read register cstrap to detect the value 2. set only bit cstrap: dcxo to ? 0 ? and set the others as detected before cstrap strap status register (d08f h ) reset value: 0000 0xxx xxxx xx10 b 15 14 13 12 11 10 9 8 res strap rw rw 7 6543210 strap dcxo iscd rw rw rw field bits type description res [15:11] rw reserved returns 0 upon read; must be written with 0. strap [10:2] rw strap pin definition this register enables the oak ? to read the strap values sampled during reset. bit function 10 pcm clock master strap 9:7 test mode strap 6 emulation boot strap 5 pll bypass strap 4 dsp pll power-down strap 3boot strap 2 reset counter bypass strap dcxo 1rw dcxo synchronization config 0 linear (slow) synchronization 1 fast synchronization (default)
peb 20570/pef 20570 peb 20571/pef 20571 delic strap option configuration addendum 8/8 2003-08-04 iscd 0rw internal source clock delay 0 pfs, pdc, dcl, fsc, dcl2000 are delayed by some ns (default) 1 pfs, pdc, dcl, fsc, dcl2000 are not delayed field bits type description
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